1. Field of the Invention
The present invention is directed in general to the field of integrated circuit design. In one aspect, the present invention relates to a method of predicting manufacturing yield of a proposed integrated circuit design.
2. Description of the Related Art
As semiconductor device geometries continue to shrink and new process materials are adopted, it is increasingly difficult for semiconductor designers to estimate and realize device yields which traditionally have been limited primarily by defect density, but which is now impacted greatly by the interaction of process-related deviations with design elements. One approach for predicting yield, called the critical area analysis (CAA), uses a “critical area” of an integrated circuit layout as a measure to reflect the sensitivity of the layout to defects created occurring during the manufacturing process by particles, such as dust and other contaminants in materials and equipment. Defects can cause different types of circuit failures. For example, “short” defects are caused by extra material that is formed to connect or “short” different conducting regions, which can occur when shapes are printed larger than designed during the manufacturing process. As another example, “open” defects can occur when shapes are printed smaller than designed during the manufacturing process and when non-conductive particles or contaminants are formed in a conducting region to create an open circuit. While the CAA yield model is useful for predicting a yield value that can be used as a tool to control chip manufacturing costs, the CAA yield model has a built-in error in failing to properly account for the effects of “partial” open and short defects. For example, consider the case where a conductive line is only partially blocked by a contaminant/particle, but the conductive line is nonetheless sufficiently conductive. If the CAA yield model accounts for this partial open defect as a yield loss, then this results in a false yield loss prediction, which in turn can lead wasted efforts to correct false yield issues. Conversely, in the case where a conductive line is only partially blocked by a contaminant/particle so that the conductive line is insufficiently conductive, but the CAA yield model waives partial open defect (i.e., does not include it as a yield loss), then this results in a yield loss not being detected, which can result in the tape out of low yield products.
Accordingly, a need exists for an improved methodology and apparatus for accurately predicting manufacturing yield of a proposed integrated circuit design. There is also a need for improved integrated design processes and systems to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional methodologies and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that elements illustrated in the figures are illustrated in diagrammatic form for simplicity and clarity. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.